1. SylabUZ
2. Wydział Informatyki, Elektrotechniki i Automatyki
3. semestr zimowy 2020/2021
4. Automatyka i robotyka - Program Erasmus pierwszego stopnia
5. Discrete process control

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Discrete process control - opis przedmiotu

Cel przedmiotu

• Familiarize students with discrete control issues in which the control algorithm is implemented as a sequential model (FSM), concurrent model (Petri net) or hierarchical model (UML state machine).
• Shaping basic skills of modelling control systems and their formal verification.

Wymagania wstępne

Zapisz zmiany

• Fundamentals of discrete systems
• Computer architecture

Zakres tematyczny

• Formal specification of discrete process at the behavioral level: flowchart, hierarchical state machine (statechart, UML state machine), hierarchical Petri net.
• Modular behavioral specification of logic control programs using hierarchical Petri nets, The role of formal specification in PLC programming.
• UML as a reactive system specification tool. UML state machine diagram, activity diagram, use case diagram. UML role in documenting and synthesis of software for embedded digital microsystems.
• Formal verification with the use of Petri net theory.
• Logic controller architecture: microcontroller as a logic controller, digital System-on-Chip (SoC) microsystems. Industrial Programmable Logic Controller (PLC). Embedded, Reconfigurable Logic Controller (RLC).
• Software or structural realization of logic controllers: RLC programming based on behavioral specifications. Structural synthesis of embedded controller using formal methods based on behavioral specification. The role of hardware description languages (e.g., VHDL, Verilog) in system synthesis.
• Specification and modeling of binary control algorithms on the system-level using UML, Petri nets and professional CAD systems for digital microsystem design.

Metody kształcenia

Lecture: conventional lecture.
Laboratory: laboratory exercises.

Efekty uczenia się i metody weryfikacji osiągania efektów uczenia się

Opis efektu	Symbole efektów	Metody weryfikacji	Forma zajęć

Warunki zaliczenia

Lecture: the main condition to get a pass are sufficient marks in written exam.

Laboratory: a condition of pass is to obtain positive grades from all laboratory exercises that are expected to be performed within the laboratory program. 

Composition of the final grade: lecture: 50% + laboratory: 50%

Literatura podstawowa

1. Rumbaugh J., Jacobson I., Booch G., The Unified Modeling Language Reference Manual, Second Edition, Addison-Wesley, USA, 1999.
2. Adamski M., Karatkevich A., Węgrzyn M., Design of Embedded Control Systems, Springer (USA), New York, 2005.
3. Żurawski R.(Ed.), Embedded Systems Handbook, CRC, Boca Raton, 2006.
4. Harel D., Feldman Y.: Algorithmics, The Spirit of Computing (3rd Edition), Addison-Wesley, USA, 2004.

Literatura uzupełniająca

1. Reisig W., Petri Nets: An Introduction, Berlin, Germany:Springer-Verlag, 2012.
2. Yakovlev, Gomes L., L. Lavagno (Ed.), Hardware Design and Petri Nets, Kluwers Academic Publishers, Boston, 2000.
3. Booch G., Rumbaugh J., Jacobson I., The Unified Modeling Language User Guide, Second Edition, Addison-Wesley, USA, 2005.
4. Bazydło G., Graphic specification of programs for reconfigurable logic controllers using Unified Modeling Language, University of Zielona Góra Press, Lecture Notes in Control and Computer Science, Zielona Góra, 2012.
5. Wiśniewski R., Prototyping of Concurrent Control Systems Implemented in FPGA Devices, Cham, Switzerland:Springer, 2017.

Uwagi

Zmodyfikowane przez dr inż. Grzegorz Bazydło (ostatnia modyfikacja: 27-04-2020 19:51)