1. SylabUZ
2. Faculty of Computer Science, Electrical Engineering and Automatics
3. winter term 2021/2022
4. Computer Science - First-cycle Erasmus programme
5. Modelling and simulation of digital systems

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Modelling and simulation of digital systems - course description

Aim of the course

• familiarize students with the standard languages of the equipment description (HDL)
• to familiarize students with the use of HDL languages for modeling, simulation, and synthesis of the digital circuits
• forming among students an understanding of the necessity of computer-based computing verification (simulation) of designed digital circuits

Prerequisites

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Digital circuits, Fundamentals of programming, Computer architecture

Scope

Introduction: Genesis and destination of hardware description languages (HDL). Introduction to modeling of digital systems. VHDL language. General organization of the design unit. Different levels of abstraction describing the architecture of the design unit. Basic instructions parallel (instructions for assigning signal values, blocks, parallel instructions calling procedures and functions). Defining processes with a sensitivity list. Instructions Sequential. Synchronization of processes. The architecture of the unit presented in the form description of behavior (behavioral). The architecture of the unit in the form of a structure description. Configurations. Concepts of constants, variables and signals. Procedures and functions. Ways of the delay modeling. Attributes, predefined attributes. Packages. Libraries. Discussion complex types (records, files). Text operations in VHDL language. Creating models testers (testbench). Verilog language. General arrangement of the layout module. Abstraction levels of the module description. Basic parallel statements (continuous and procedural assignments, task calls and functions). Always and initial constructions. Sequential instructions. Modules. Models of systems in the form of structure description. Constants, networks and registers. Ways of delay modeling. The use of multivalent logic (high impedance modeling, creation
three-state bus). Modeling of CMOS circuits. Standard gates and buffers. UDP systems: combinational and sequential. Tasks and functions. Tasks and system functions. Defining your own tasks and functions. Text operations in the Verilog language. The use of HDL languages for the synthesis of digital circuits. Modeling of machines digital. Strategies for designing digital systems in VHDL language. Sharing resources system. Delays in simulation and synthesis. Simulation including
real delay (backannotation). Modeling of hardware and software systems. The basics of the SystemVerilog language.

Teaching methods

• Lecture: conventional / traditional lecture
• Laboratory: laboratory exercises using computer equipment

Learning outcomes and methods of theirs verification

Outcome description	Outcome symbols	Methods of verification	The class form

Assignment conditions

• Lecture - the condition for passing is to obtain positive mark from final test
• Laboratory - the condition for passing is to get positive grades from everyone laboratory exercises planned for implementation as part of the laboratory program, and knowledge tests, minimum two
• Components of the final grade = lecture: 50% + laboratory: 50%

Recommended reading

1. Zwoliński M., Digital System Design with VHDL, Prentice-Hall, Inc, 2003
2. Bergeron J., Writing Testbenches, Functional Verification of HDL Models, Springer 2013
3. Bergeron J.: Writing Testbenches using SystemVerilog, Springer, New York, 2006
4. Mehta, Ashok B., Introduction to SystemVerilog, Springer, 2021

Further reading

1. Cohen B.: VHDL Coding Styles and Methodologies, Kluwer Academic Publishers, Second Printing, 1996
2. IEEE Std 1364-2001: IEEE Standard Verilog Hardware Description Language, IEEE, Inc., New York, USA

Notes

Modified by dr inż. Michał Doligalski (last modification: 13-09-2021 22:42)